DRAM semiconductor memory devices generally have a higher density of integration than do SRAM semiconductor memory devices. However, DRAM memory devices require that a refresh operation be periodically performed in order to prevent data loss and thus DRAM memory devices consume power even when in a stand-by mode. It is not necessary to perform a refresh process with nonvolatile memory devices such as a flash memory devices. However, nonvolatile memory devices may require a higher voltage to perform a write operation.
In order to overcome the drawbacks of DRAM memory devices and nonvolatile memory devices, semiconductor memory devices using multi-tunnel junction patterns are suggested as disclosed, for example, in U.S. Pat. No. 5,952,692, entitled “Memory Device With Improved Charge Storage Barrier Structure” and U.S. Pat. No. 6,169,308, entitled “Semiconductor Memory Device And Manufacturing Method Thereof.” An example of a semiconductor memory device that uses multi-tunnel junction patterns is shown FIGS. 1 and 2, which are a cross-sectional view and a circuit diagram thereof, respectively.
Referring to FIGS. 1 and 2, a unit cell of the semiconductor memory device comprises a vertical transistor TR1 and a planar transistor TR2. The planar transistor TR2 has a source region 39s, a drain region 39d and a floating gate 6, where the source/drain regions 39s and 39d are formed in a predetermined region of a semiconductor substrate 2 to be spaced apart from each other and the floating gate 6 is disposed on the channel region between the source and drain regions 39s and 39d. The drain region 39d corresponds to a bit line and the floating gate 6 corresponds to a storage node. A gate insulator 4 is interposed between the storage node 6 and the channel region.
As shown in FIG. 1, a multi-tunnel junction pattern 16 and a data line 27 are sequentially stacked on the storage node 6. The multi-tunnel junction pattern 16 comprises a semiconductor layer 8 and a tunnel insulating layer 10 stacked repeatedly and sequentially. The top layer 12 of the multi-tunnel junction pattern 16 may be one of the semiconductor layers 8 or one of the tunnel insulating layers 10. The data line 27 extends to connect electrically with a plurality of adjacent memory cells (not shown in FIGS. 1 and 2). The storage node 6, the multi-tunnel junction pattern 16 and the data line 27 constitute a multi-layered pattern.
As is also shown in FIG. 1, a gate inter-layer insulator 40 covers the side and top surfaces of the multi-layered pattern. A word line 42 is disposed on the gate inter-layer insulator 40 to cross the data line 27 and other multi-layered patterns. The data line 27, the multi-tunnel junction pattern 16, the storage node 6 and the word line 42 constitute the vertical transistor TR1.
The semiconductor memory cell depicted in FIGS. 1 and 2 operates as follows. First, a data voltage and a write voltage are applied to the data line 27 and the word line 42, respectively, during a writing mode. This acts to form an inversion channel at the sidewalls of the semiconductor layer 8 to generate a tunneling current flowing through the tunnel insulating layer 10. As a result, electric charges such as electrons and holes are stored in the storage node 6 to change the threshold voltage of the planar transistor TR2, where the quantity of electric charges depends on a voltage applied to the data line 27.
Next, for reading data stored in the storage node 6, a reading voltage is applied to the storage node 6 and a suitable voltage, for example the ground voltage, is applied to the source region 39s. If the threshold voltage of the planar transistor TR2 is higher than the reading voltage, the planar transistor TR2 enters a turn-off state, and no current flows through the drain region 39d. On the contrary, if the threshold voltage of the planar transistor TR2 is lower than the reading voltage, the planar transistor TR2 enters a turn-on state and current flows through the drain region 39d. The storage node 6 acts as the gate of the planar transistor TR2 during the reading operation, and the reading voltage applied to the storage node 6 depends on a voltage applied to the word line 42 and a coupling ratio.
According to the above-described prior art, during the writing operation, the threshold voltage of the planar transistor TR2 changes depending on the quantity of electric charges stored in the storage node 6. Meanwhile, the reading operation comprises sensing a quantity of electric charges flowing through the channel region of the planar transistor TR2, where the quantity of electric charges flowing through the channel region of the planar transistor TR2 changes depending upon the threshold voltage of the planar transistor TR2. However, if electric charges stored in the storage node 6 are insufficient, a higher voltage may be needed for the word line in the reading operation. If the voltage applied to the word line is higher, a channel region may be formed in the vertical transistor which may result in leakage of the electric charges stored in the storage node 6.